Icarus Verilog
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The basic format of a command file is one source file or compiler argument per line. Command files may also have comments of various form, and options for controling the compiler.

Comments

Lines that start with a "#" character are comments. All text after the "#" character, is ignored.

The "//" character sequence also starts a comment that continues to the end of the line.

The "/*" and "*/" character sequences surround multi-line comments. All the text between the comment start and comment end sequences is ignored, even when that text spans multiple lines. This style of comment does not nest, so a "/*" sequence within a multi-line comment is probably an error.

Plus-args

Outside of comments, lines that start with a "+" character are compiler arguments. These are called plusargs but they are not the same as extended arguments passed to the "vvp" command. The supported plusargs are definitively listed in the iverilog manual page.

The plusargs lines are generally "+<name>+..." where the name is the name of an switch, and the arguments are separated by "+" characters, as in:

+libext+.v+.V+.ver

With plusargs lines, the "+" character separates tokens, and not white space, so arguments, which may include file paths, may include spaces. A plusarg line is terminated by the line end.

The line in the command file may also be a "-y" argument. This works exactly the same as the:

-y <path>

argument to the compiler; it declares a library directory. The "-y" syntax is also a shorthand for the "+libdir" plusarg, which is a more general form.

+libdir+<path>...

File Names

Any lines that are not comments, compiler arguments or plusargs are taken by the compiler to be a source file. The path can contain any characters (other then comment sequences) including blanks, although leading and trailing white space characters are stripped. The restriction of one file name per line is in support of operating systems that can name files any which way. It is not appropriate to expect white spaces to separate file names.

Variable Substitution

The syntax "$(name)" is a variable reference, and may be used anywhere within filenames or directory names. The contents of the variable are read from the environment and substituted in place of the variable reference. In Windows, these environment variables are the very same variables that are set through the Control~Panel->System dialog box, an in UNIX these variables are environment variables as exported by your shell.

Variables are useful for giving command files some installation independence. For example, one can import a vendor library with the line:

-y $(VENDOR)/verilog/library

in the command file, and the next programmer will be able to use thiscommand file without editing it to point to the location of VENDOR on his machine. Note the use of forward slashes as a directory separator. This works even under Windows, so always use forward slashes in file paths and Windows and UNIX users will be able to share command files.

Summary

This sample:

# This is a comment in a command file.
# The -y statement declares a library
# search directory
-y $(PROJ_LIBRARY)/prims
#
# This plusarg tells the compiler that
# files in libraries may have .v or .vl
# extensions.
+libext+.v+.vl
#
main.v // This is a source file
#
# This is a file name with blanks.
C:/Project Directory/file name.vl

is a command file that demonstrates the major syntactic elements of command files. It demonstrates the use of comments, variables, plusargs and file names. It contains a lot of information about the hypothetical project, and suggests that command files can be used to describe the project as a whole fairly concisely.

The syntax of command files is rich enough that they can be used to document and control the assembly and compilation of large Verilog programs. It is not unusual to have command files that are hundreds of lines long, although judicious use of libraries can lead to very short command files even for large designs. It is also practical to have different command files that pull together combinations of sources and compiler arguments to make different designs from the same Verilog source files.

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