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== Using Icarus Verilog ==
  +
 
=== How do I debug a Verilog design with Icarus - there is no built in waveform viewer like Mentor? ===
  
=== How do I debug a Verilog design with Icarus - there is no built in waveform viewer like Mentor? ===
   
−
Verilog has a standard dump format called [[Glossary#VCD|VCD]] that is used to dump the state of the design as it simulates. Use the $dumpfile directive to create a file that contains the dump state. Use the $dumpvars directive to define the scope of the dump.
 +
Verilog has a standard dump format called [[Glossary#VCD|VCD]] that is used to dump the state of the design as it simulates. Use the $dumpfile directive to create a file that contains the dumped waveforms. Use the
  +
$dumpvars directive to define the scope of the dump. The example below
  +
dumps everything in and below the test module.
   
 
Example:
  
Example:
Line 13: Line 17:
 
end
  
end
   
−
Once you have the dump file you can use a wave form viewer like [[GTKWAVE]] to look at the state.
 +
Once you have the dump file you can use a wave form viewer like [[GTKWAVE]] or [[dinotrace]]
  +
or [THIS URL IS DEAD [http://www.iss-us.com/wavevcd/index.htm Wave VCD viewer]]
  +
  +
=== Gracious, my VCD files are ''huge''. Isn't there a better way? ===
  +
  +
Indeed there is. If you are using [[GTKWAVE]] for waveform display, you can
  +
dump your waves in LXT2 format or fst. LXT2 and fst are compact binary formats that are
  +
fast to write and fast to read. There are two ways to enable these outputs:
  +
  +
* Set the environment variable IVERILOG_DUMPER to "lxt2" or "fst", or
  +
* Pass the "-lxt2" or "-fst" flag as an extended argument to the [[Vvp_Flags|vvp]] command.
  +
  +
Then use the GTKWAVE command to open the lxt2 file. Note that GTKWAVE
  +
generally expects that LXT2 files have the ".lxt" suffix, so you may have to
  +
change your "$dumpfile" system task call to give a file name with the
  +
right suffix.
   
 
=== Where do I get [[GTKWAVE]]? ===
  
=== Where do I get [[GTKWAVE]]? ===
   
−
GTKWAVE can be found several places - but the Icarus.com site has several versions avaiable [ftp://ftp.icarus.com/pub/eda/gtkwave at this ftp site].
 +
GTKWAVE can be found several places - but the Icarus.com site has several versions available [ftp://ftp.icarus.com/pub/eda/gtkwave at this ftp site].
  +
  ⚫
The home page for GTKWAVE is [http://gtkwave.sourceforge.net/ here],
  +
and is the place to go for the most current version.
  +
  +
=== What about synthesis? ===
  +
  +
Way back in the olden days, Icarus Verilog did indeed support synthesis, but that
  +
support has faded away. The last workable synthesis support was in versions 0.8.
  +
Starting in versions 0.9 to the current date, synthesis has been more or less dropped.
  +
It turns out that there is more than enough work to do catching up with the latest
  +
Verilog, SystemVerilog, Veriog-A/MS and VHDL to keep the current developers busy
  +
for the rest of our days. Combine that with a lack of real interest in workable
  +
synthesis in Icarus Verilog, and that FPGA vendors typically provide free synthesis
  +
tools, and the incentives are just not there.
  +
  +
For an actively maintained open source Verilog synthesis tool, see [http://www.clifford.at/yosys/ yosys].
  +
  +
== About The Icarus Verilog Project ==
  +
  +
=== How can I help? ===
  +
  +
Well, one obvious way is for you to contribute to this
  +
Wiki. This is the main user level documentation for the
  +
Icarus Verilog software, so improving it is bound to be
  +
valuable.
  +
  +
If you are skilled in Verilog but not C/C++, another useful
  +
form of contribution is bug reports and regression tests.
  +
Go to the
  +
[http://iverilog.icarus.com Icarus Verilog]
  +
home page and follow the links to the bug tracking
  +
database. The bug tracking database is hosted on
  +
sourceforge.net.
  +
  +
The regression test suite has a bug tracker at the
  +
[http://sourceforge.net/projects/ivtest ivtest]
  +
project on sourceforge, although the files are stored in
  +
a git repository in github. Contributions here are
  +
very helpful. See the [[Developer Guide]]for details on
  +
how to access the regression test suite.
  +
  +
If you are skilled in C/C++, then there are several major
  +
components that are varying levels of complexity to work
  +
in, including the system task/function implementations,
  +
the vvp run time engine, the various code generators, and
  +
the compiler itself.
  +
Read the [[Projects]] and [[Graffiti]] pages for suggestions.
  +
  +
=== How can I contribute? ===
  +
  +
If your time is limited and you would rather throw money
  +
at the project, there is a
  +
[http://iverilog.icarus.com/donations donations]
  +
link accessible from the Icarus Verilog home page. This
  +
link is for open-ended donations of money.
  +
  +
And in certain cases, if you desire a specific feature
  +
or specific form of technical support, the author, and
  +
possibly others, may be available for hire. Go to the
  +
Icarus Verilog support page and look for
  +
"Commercial Support." A direct link to the support page is
  +
[http://iverilog.icarus.com/support here].
  +
  +
=== How can I complain? ===
  +
  +
There is a bug tracker and a feature request tracker for submitting
  +
bug reports. Go to the [http://iverilog.icarus.com/support/bugs bugs]
  +
page to read how to prepare a good bug report. That page will then
  +
send you to the actual bug tracker (on sourceforge.net) where you
  +
can submit your report and look at others.
  +
  +
=== Future Plans ===
   
  +
See the [[Development Time Line]] for our current thinking on
⚫
The home page for GTKWAVE is [http://home.nc.rr.com/gtkwave/ here].
  
  +
where we are going with Icarus Verilog.

Latest revision as of 03:21, 20 October 2020

Using Icarus Verilog[]

How do I debug a Verilog design with Icarus - there is no built in waveform viewer like Mentor?[]

Verilog has a standard dump format called VCD that is used to dump the state of the design as it simulates. Use the $dumpfile directive to create a file that contains the dumped waveforms. Use the $dumpvars directive to define the scope of the dump. The example below dumps everything in and below the test module.

Example: 

// Do this in your test bench

initial
 begin
    $dumpfile("test.vcd");
    $dumpvars(0,test);
 end

Once you have the dump file you can use a wave form viewer like GTKWAVE or dinotrace or [THIS URL IS DEAD Wave VCD viewer]

Gracious, my VCD files are huge. Isn't there a better way?[]

Indeed there is. If you are using GTKWAVE for waveform display, you can dump your waves in LXT2 format or fst. LXT2 and fst are compact binary formats that are fast to write and fast to read. There are two ways to enable these outputs:

  • Set the environment variable IVERILOG_DUMPER to "lxt2" or "fst", or
  • Pass the "-lxt2" or "-fst" flag as an extended argument to the vvp command.

Then use the GTKWAVE command to open the lxt2 file. Note that GTKWAVE generally expects that LXT2 files have the ".lxt" suffix, so you may have to change your "$dumpfile" system task call to give a file name with the right suffix.

Where do I get GTKWAVE?[]

GTKWAVE can be found several places - but the Icarus.com site has several versions available at this ftp site.

The home page for GTKWAVE is here, and is the place to go for the most current version.

What about synthesis?[]

Way back in the olden days, Icarus Verilog did indeed support synthesis, but that support has faded away. The last workable synthesis support was in versions 0.8. Starting in versions 0.9 to the current date, synthesis has been more or less dropped. It turns out that there is more than enough work to do catching up with the latest Verilog, SystemVerilog, Veriog-A/MS and VHDL to keep the current developers busy for the rest of our days. Combine that with a lack of real interest in workable synthesis in Icarus Verilog, and that FPGA vendors typically provide free synthesis tools, and the incentives are just not there.

For an actively maintained open source Verilog synthesis tool, see yosys.

About The Icarus Verilog Project[]

How can I help?[]

Well, one obvious way is for you to contribute to this Wiki. This is the main user level documentation for the Icarus Verilog software, so improving it is bound to be valuable.

If you are skilled in Verilog but not C/C++, another useful form of contribution is bug reports and regression tests. Go to the Icarus Verilog home page and follow the links to the bug tracking database. The bug tracking database is hosted on sourceforge.net.

The regression test suite has a bug tracker at the ivtest project on sourceforge, although the files are stored in a git repository in github. Contributions here are very helpful. See the Developer Guidefor details on how to access the regression test suite.

If you are skilled in C/C++, then there are several major components that are varying levels of complexity to work in, including the system task/function implementations, the vvp run time engine, the various code generators, and the compiler itself. Read the Projects and Graffiti pages for suggestions.

How can I contribute?[]

If your time is limited and you would rather throw money at the project, there is a donations link accessible from the Icarus Verilog home page. This link is for open-ended donations of money.

And in certain cases, if you desire a specific feature or specific form of technical support, the author, and possibly others, may be available for hire. Go to the Icarus Verilog support page and look for "Commercial Support." A direct link to the support page is here.

How can I complain?[]

There is a bug tracker and a feature request tracker for submitting bug reports. Go to the bugs page to read how to prepare a good bug report. That page will then send you to the actual bug tracker (on sourceforge.net) where you can submit your report and look at others.

Future Plans[]

See the Development Time Line for our current thinking on where we are going with Icarus Verilog.

Community content is available under CC-BY-SA unless otherwise noted.