Icarus Verilog
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Forums: Index > Help desk > Signed/unsigned



(Nevermind, updating to the most recent version seemed to fix it.)

Hi,

I am wondering if someone can help me understand the following behavior:

 reg signed [3:0] start, result;
 initial begin
 start = 4'b1000;
 result = start >>> 1;
 $display("result = %b", result);
 $finish;

this prints 1110, which is what I expect, however if I change this slightly so that instead

 result = (4'sb1000) >>> 1;
 

then I get 0000, which is something that I did not expect.

Any insight would be much appreciated.

Thanks.

-Mike

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