Icarus Verilog
Icarus Verilog
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module sum_n_natural_numbers(

    input [31:0] n,

    output reg [31:0] sum

);

    integer i;

    always @(*) begin

        sum = 0;

        for (i = 1; i <= n; i = i + 1) begin

            sum = sum + i;

        end

    end

endmodule

`timescale 1ns / 1ps

module tb_sum_n_natural_numbers;

    reg [31:0] n;

    wire [31:0] sum;

    sum_n_natural_numbers uut (

        .n(n),

        .sum(sum)

    );

    initial begin

        n = 5; #10; $display("Sum of first %d natural numbers: %d", n, sum);

        n = 10; #10; $display("Sum of first %d natural numbers: %d", n, sum);

        n = 0; #10; $display("Sum of first %d natural numbers: %d", n, sum);

        n = 1; #10; $display("Sum of first %d natural numbers: %d", n, sum);

        n = 100; #10; $display("Sum of first %d natural numbers: %d", n, sum);

        $finish;

    end

endmodule

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