module traffic_light(
input clk,
input rst,
output reg red,
output reg yellow,
output reg green
);
// Define states
parameter [1:0] S_RED = 2'b00;
parameter [1:0] S_YELLOW = 2'b01;
parameter [1:0] S_GREEN = 2'b10;
// Define state register
reg [1:0] state;
// Define state machine
always @(posedge clk or posedge rst) begin
if (rst) begin
state <= S_RED; // Initial state
end else begin
case (state)
S_RED: begin
red <= 1;
yellow <= 0;
green <= 0;
state <= S_YELLOW;
end
S_YELLOW: begin
red <= 0;
yellow <= 1;
green <= 0;
state <= S_GREEN;
end
S_GREEN: begin
red <= 0;
yellow <= 0;
green <= 1;
state <= S_RED;
end
default: state <= S_RED;
endcase
end
end
endmodule