Icarus Verilog

module tb;

  logic [1:0] a;

  logic [1:0] b;

  logic [1:0] c;

  logic s0, s1;

  logic [1:0] y;

  assign y = s0 ? s1 ? a : b : c;

  initial begin

    s0 = 0;

    s1 = 0;

    a = 0;

    b = 1;

    c = 2;

    #1; $display("%d %d %d", s0, s1, y);

    s0 = 1;

    #1; $display("%d %d %d", s0, s1, y);

    s0 = 0;

    s1 = 1;

    #1; $display("%d %d %d", s0, s1, y);

    s0 = 1;

    #1; $display("%d %d %d", s0, s1, y);

  end

endmodule