module dff (
input wire d, // Data input input wire clk, // Clock input input wire rst_n, // Active-low reset output reg q // Output
);
// On clock edge, check for reset and latch data always @(posedge clk or negedge rst_n) begin if (!rst_n) q <= 0; // Reset the output to 0 else q <= d; // Latch the input data end
endmodule