Icarus Verilog

This glossary defines various terms related, sometimes indirectly, to Icarus Verilog.



This is an acronym for "Concurrent Versioning System". It is a widely used source code management system. It's home page is here.



This is an acronym for "Electronics Design Interchange Format". It is a common netlist format. It is standard number ANSI/EIA-548 published by the Electronics Industries Alliance(EIA).

For complete detail on EDIF, see the Wikipedia entry here.


The act of instantiating the elements of a design. The user specifies some top level modules (called "root instances") and elaboration is the process of finding their definitions, creating instances, finding their children and instantiating those recursively. Elaboration includes resolving parameters overriden by instantiation and by defparam statements. The elaborated design is usually what is used by tools like synthesis and simulation.

In Icarus Verilog it is the phase of processing Verilog source between parsing and code generation. Compiler theorists call this "Semantic Analysis". In Verilog processing, the elaboration happens (conceptually) after parsing and before any optimizations and code generation.

The user doesn't directly see the results of elaboration, but the word is used when describing where or why an error message came from the compiler.



No one, not even the author of git, quite knows what "git" stands for. It's a source code management system that is sometimes a little more opaque than CVS, but is generally more powerful. Its home page, including documentation, is here.


lxt / lxt2[]

This is a waveform dump format that is unique to the GTKWave waveform viewer. It is a more compact format then the default VCD format, but is not as widespread. However, the GTKWave viewer is free, open and portable. Icarus Verilog supports the lxt and lxt2 format.



The output of an EDA tool that describes the connectivity of a network of components. This meaning is obvious when it is produced by a schematic editor. HDL synthesizers also produce netlists to describe the compiled result.

Icarus Verilog also sometimes produces netlists (i.e. if synthesis is requested) and keeps the elaborated design internally in a form like a netlist. Note that the term "netlist" is not typically used when talking about simulation.



Acronym Programming Language Interface. This is the standardized interface provided by compliant Verilog simulators. PLI 1 is the standard name for the "tf_" and "acc_" functions, and PLI 2 (also called "VPI") is the more recent standard API.



Acronym for Value Change Dump. It notes the changes in signal values for a simulation in an external file so that waveform viewers can view the results. This dump format is defined by the Verilog standard, and so is most ubiquitous.


Verilog Programmer Interface. Also called PLI 2. See PLI above.