Here are the release notes for Icarus Verilog release branch 0.9. The 0.9 release is a huge improvement over the 0.8 release series, in every aspect (except synthesis). Much more of the Verilog language is supported, many bugs have been fixed, and performance has improved. The changes (improvements!) are so numerous that there is no point attempting to enumerate them.

Release notes for later versions within the 0.9 series are here:

The Transition: New Versioning and Packaging Process Edit

Since Icarus Verilog 0.9 is such a leap from 0.8, we've defined a transition process that allows users to advance to 0.9 incrementally. To support the transition, the Icarus Verilog 0.9 series starts a new process for managing versions and the head of the older 0.8 branch is modified to conform. The idea is to allow older versions of Icarus Verilog to co-exist on a system with the current version. For this to work, the build process adds support for installation suffixes.

As Icarus Verilog 0.9 becomes the current version, Icarus Verilog 0.8 becomes a legacy release. The build for the current version (0.9) does not compile in a suffix and installs as usual. The head of the legacy release (0.8), however, does build in the suffix by default, and packages are expected to install the legacy head with the suffix intact, and with a new package name so that it can be installed along with 0.9. This should allow users to install packages for both 0.8.7 and 0.9.x without confusing package managers.

Major New Features Edit

The changes that lead to Icarus Verilog 0.9 can be divided into a few major categories shown below.

Language Coverage Edit

The biggest new feature is that IEEE1364-2005 language coverage has been much increased. Icarus Verilog development is working towards the -2005 version of IEEE1364, and the great majority of the language is now supported. Also, Icarus Verilog is better about reporting errors for things that are invalid.

Some examples of better language coverage:

  • Support for standard uses of real and realtime variables is complete.
  • Values are converted as need (real -> bit based and bit based -> real).
  • Full support for power operator.
  • Signed vector support is fixed up and completed.
  • Arrays of variables and arrays of nets (wires) is more complete. (Multi-dimensional arrays are still not supported.)
  • All standard generate schemes are supported.
  • Most file I/O system tasks/functions are supported ($ferror, $fread and $fmonitor are currently missing).
  • IEEE1364-2005 math system functions are supported.
  • Limited specify block and SDF support. All unsupported specify block items should be ignored (timing checks, etc.).
  • System tasks/functions are much more thorough about checking their arguments and printing useful error messages.
  • Switch modeling (tran/tranif) is now supported.
  • CMOS switches are supported (cmos/rcmos).
  • All delays should be 64-bit clean.
  • Support for all the probabilistic distribution functions.
  • Support for a concatenation with a zero repetition count where allowed by the standard.
  • Fully support intra-assignment event control.
  • Check always blocks for infinite loops (error) or possible infinite loops (warning).
  • Support for automatic tasks and functions.
  • Functions and task should support all expected argument types.
  • Support for macros with arguments.
  • Support for force/release and assign/deassign has been enhanced.

Language Extensions Edit

Icarus Verilog is also working beyond the base IEEE1364 to include extensions from other related languages, including SystemVerilog (IEEE1800) and Verilog-AMS. The command line flags "-gXXXX" have been reorganized to account for the various extensions that are available.

Some examples of new language extensions implemented:

  • Support for real-valued nets.
  • Support for "logic" and "bool" net and variable types.
  • Verilog-AMS math function keywords are supported.
  • Verilog-AMS $simparm/$simparam_str are partially supported.
  • Verilog-AMS $abstime is supported.
  • Library modules inherit preprocessor macros from the main elaboration phase.
  • VHDL code generator for translating to VHDL.
  • $urandom/$urandom_range for System Verilog.
  •  %v of a vector returns the strength of all the bits separated by an underscore.

Runtime Rework Edit

The Icarus Verilog run-time has been largely redone from the 0.8 legacy. The internal representations of data and data types has been redone, and the discrete event simulation engine has been cleaned up. The consequence of this is that performance of some kinds of designs should improve significantly, although some other (hopefully less common) designs may suffer slightly. This rework should not have an obvious visible effect for users.

Code Generator API Rework Edit

The rework of other parts of the compiler has led, naturally, to a rework of the ivl_target.h code generator API. This means that code generators for the 0.8 series will not work with the 0.9 series. We do not know of any commonly used 3rd party code generators that would be impacted by this, so we doubt this will have significant impact.

General Bug Fixes Edit

There are many changes that count as bug fixes. They change the behavior to better conform to the standard, or fix plain broken behavior. Some major examples include:

  • Many fixes to the calculation of expression bit widths.
  • Type management vis a vis signed vs. unsigned vs real is straightened out for many expression operators.
  • Plug a variety of memory leaks during compile time and run time.
  • Cleaned up the source code configuration process.
  • Greatly improved the reporting of the versions of parts of the compiler.
  • Many fixes/enhancements to the PLI (VPI) interface.

Things That Still Don't Work Edit

Icarus Verilog is an ongoing and very active project, so the commonly used features are all in pretty good shape, but there are still areas where Icarus Verilog is not complete. You may never need any of these missing capabilities, but then again your line of work may bring you right up against these issues.

Synthesis Edit

In previous version of Icarus Verilog there was basic support for synthesis. In the development of V0.9 a significant amount of the underlying code was changed and this has broken many/most of the synthesis routines. This is expected to be fixed in a future Icarus release, but until then the V0.8 branch should be used for synthesis.

Missing Language Features Edit

  • PLA modeling system tasks.
  • Stochastic analysis system tasks.
  • Multi-dimensional arrays.
  • Timing checks (they are currently ignored).
  • Inertial delays and the various pulse limits.
  • Constant user functions.
  • Net delays.
  • trireg nets (capacitive networks).

Bugs Still Pending Edit

There are known bugs that are still pending. Some will be fixed in later releases of 0.9, and some will have to wait for the next major release. See the bug tracker for the current list.

Where to Get Icarus Verilog 0.9 Edit

The source tarball is available from the main ftp site: <>. There are also precompiled packages for select systems. Or look at the standard software distribution sites for your operating system.