This is an update to the Icarus Verilog 0.9 release series. If you are new to v0.9 in general, then you may want to refer back to these older release notes since this page only covers the differences between v0.9.6 and v0.9.7.
Major New Features
Within the v0.9 series we try to keep the major changes to a minimum, but some new features are allowed in if we feel that they do not risk the stability of the branch or of Verilog programs that use this compiler.
General Bug Fixes
- Update lxt2/fst dumpers from latest GTKWave
- Numerous other bug fixes (the complete details can be found in the commit logs for the v0_9-branch of iverilog on github).
Things That Still Don't Work
This isn't necessarily a complete list of missing features, but this should at least list the missing features that you are likely to encounter.
Missing Language Features
- PLA modeling system tasks.
- Multi-dimensional arrays.
- Timing checks (they are currently ignored).
- The various pulse limits/controls.
- specparam with a range, outside a specify block, back-annotation, or referencing another specparam.
- Constant user functions.
- Net delays.
- trireg nets (capacitive networks).
- Inertial delays from the PLI
Bugs fixed/enhancements in development that will not be added to V0.9
This list has become too large to publish. Please see the git commit logs for the details.
Bugs Still Pending
There are known bugs that are still pending. Some may be fixed in later releases of 0.9, but most will have to wait for the next major release. See the bug tracker for the complete list.
Where to Get Icarus Verilog 0.9.7
The source tar file and precompiled packages for select systems are available from the main ftp site: <ftp://ftp.icarus.com/pub/eda/verilog/v0.9/>. If you don't find what you are looking for there please look on the standard software distribution site(s) for your operating system if such a thing exists. A package for Microsoft Windows can be found here: <http://bleyer.org/icarus>.