Here are the release notes for Icarus Verilog release branch 10. The 10 release is a huge improvement over the 0.9 release series, in every aspect. Much more of the Verilog and SystemVerilog language is supported, many bugs have been fixed, and performance has improved. The changes (improvements!) are so numerous that there is no point attempting to enumerate them.

Release notes for later versions within the 10 series are here:

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Major New Features[edit | edit source]

The changes that lead to Icarus Verilog 10 can be divided into a few major categories shown below.

Language Coverage[edit | edit source]

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Language Extensions[edit | edit source]

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Runtime Rework[edit | edit source]

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Code Generator API Rework[edit | edit source]

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General Bug Fixes[edit | edit source]

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Things That Still Don't Work[edit | edit source]

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Synthesis[edit | edit source]

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Missing Language Features[edit | edit source]

  • PLA modeling system tasks.
  • Timing checks (they are currently ignored).
  • Inertial delays and the various pulse limits.
  • Net delays.
  • trireg nets (capacitive networks).

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Bugs Still Pending[edit | edit source]

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Where to Get Icarus Verilog 10[edit | edit source]

The source tarball is available from the main ftp site: <ftp://ftp.icarus.com/pub/eda/verilog/v10/>. There are also precompiled packages for select systems. Or look at the standard software distribution sites for your operating system.

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