Here are the release notes for Icarus Verilog release branch 11. The 11 release extends support for the Verilog and SystemVerilog languages as well as fixing many bugs.

Release notes for later versions within the 11 series are here:

  • <none available>

Major New Features[edit | edit source]

The changes that lead to Icarus Verilog 11 can be divided into a few major categories shown below.

Verilog Language Coverage[edit | edit source]

The following Verilog language features are now supported:

  • rtran switches

SystemVerilog Language Coverage[edit | edit source]

The following SystemVerilog language features are now supported:

  • the always_comb, always_ff, and always_latch constructs
  • the case_priority and case_unique statements
  • immediate assertions
    • $assertcontrol is not supported, but you can globally disable assertions at compile time using the iverilog -gno-assertions flag
  • compilation units
    • use the iverilog -u flag to treat each source file as a separate compilation unit
  • the $countbits, $countones, $isunknown, $onehot, $onehot0 system functions

User VPI Module Support[edit | edit source]

It is now possible to specify the path to user VPI modules using the iverilog -L flag. This allows the compiler to automatically determine the return type of user-defined system functions by loading and analysing the VPI modules. The old mechanism of specifying the function return types in System Function Table (.sft) files is still supported, but deprecated.

The VPI module names and locations are automatically passed to vvp, so do not need to be specified again on the vvp command line.

Synthesis[edit | edit source]

Most of the synthesis transformations (enabled by the iverilog -S flag) that were lost in the transition from v0.8 to v0.9 have been reimplemented. Note that this functionality is only used by certain specialised back-end targets, and does not make Icarus Verilog a general-purpose synthesis tool.

Things That Still Don't Work[edit | edit source]

Missing Verilog Language Features[edit | edit source]

  • PLA modeling system tasks.
  • Timing checks (they are currently ignored).
  • Inertial delays and the various pulse limits.
  • Net delays.
  • trireg nets (capacitive networks).

Missing SystemVerilog Language Features[edit | edit source]

This is still too large a list to enumerate.

Bugs Still Pending[edit | edit source]

See the open issues on GitHub and the old bug tracker on SourceForge.

Where to Get Icarus Verilog 11[edit | edit source]

The source tarball is available from the main ftp site:<ftp://ftp.icarus.com/pub/eda/verilog/v11/>.

There are also pre-compiled packages for select systems. Or look at the standard software distribution sites for your operating system.

Community content is available under CC-BY-SA unless otherwise noted.