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Installation Guide
Icarus may be installed from source code or from pre-packaged binary distributions. Icarus is developed for Unix-like environments but can also be compiled on Windows systems using the Cygwin environment or MinGW compilers -
Getting Started
Before getting started with actual examples, here are a few notes on conventions. First, command lines and sequences take the same arguments on all supported operating environments, including Linux, Windows and the various Unix systems -
Main Page
This is the main page for the Icarus Verilog[1] documentation. From here, branch out to the different sorts of documentation you are looking for. In all cases, the documentation is in wiki form, so -
User Guide
This is the user guide: a collection of articles on how to use Icarus Verilog effectively. The two major parts cover working with Icarus Verilog and Icarus Verilog details. The first part contains articles that -
Simulation
Simulation is the process of creating models that mimic the behavior of the device you are designing (simulation models) and creating models to exercise the device (test benches). The simulation model need not reflect any -
Iverilog Flags
The iverilog command is the compiler/driver that takes the Verilog input and generates the output format, whether the simulation file or synthesis results. This information is at least summarized in the iverilog man page -
Verilog Portability Notes
Here we document Verilog language details that may be different from common Verilog tools, or standard, baseline Verilog. These are issues that may effect portability with other Verilog compilers, or may just be clarifications where -
Using VPI
Icarus Verilog implements a portion of the PLI 2.0 API to Verilog. This allows programmers to write C code that interfaces with Verilog simulations to perform tasks otherwise impractical with straight Verilog. Many Verilog -
Installation using MSYS2
Icarus Verilog source can be compiled with the MinGW-w64 C/C++ compilers to get a standalone Windows binary. This is the preferred Windows distribution form. The configure scripts automatically detect that the compilers in -
GTKWave
GTKWave is a VCD waveform viewer based on the GTK library. This viewer support VCD and LXT formats for signal dumps. The home page for GTKWAVE is here. -
Using VHDL Code Generator
Icarus Verilog contains a code generator to emit VHDL from the Verilog netlist. This allows Icarus Verilog to function as a Verilog to VHDL translator. To translate a Verilog program to VHDL, invoke "iverilog" with -
Command File Format
The basic format of a command file is one source file or compiler argument per line. Command files may also have comments of various form, and options for controlling the compiler. Lines that start with -
FAQ
Verilog has a standard dump format called VCD that is used to dump the state of the design as it simulates. Use the$dumpfile directive to create a file that contains the dumped waveforms. Use the$dumpvars -
Introduction
This chapter summarizes the place of the Verilog hardware description language in the greater task of digital electronics design. The details of the steps from algorithm to implementation vary amongst the suppliers of design tools -
Vvp Flags
The vvp command is the simulation run-time engine. The command line for vvp execution is first the options and flags, then the vvp input file, and finally extended arguments.% vvp flags foo.vvp extended -
A Horrible Idea Multithreaded Verilog Simulator
Multicore processors are the future of computing. With that in mind, we should consider how to create a multithreaded VVP simulator. The core of Verilog simulation is the handling of events. In spite of modelling -
Graffiti
Welcome to the graffiti section of the Icarus Verilog documentation. The ground rules here are a little different from the remainder of the iverilog wiki. This page is an experiment. The idea is to have -
Projects
This page is a collection of suggested projects for Icarus Verilog. People looking for something to work on can come here to find thought out and ranked suggestions. People who would like to see something -
Developer Guide
This guide is intended to help you get started working with the Icarus Verilog source code, beyond simply compiling it. If all you want is to get and compile the code on your system, see -
Release Notes Icarus Verilog 0 9
Here are the release notes for Icarus Verilog release branch 0.9. The 0.9 release is a huge improvement over the 0.8 release series, in every aspect (except synthesis). Much more of the -
Installation using MinGW
NOTE: These instructions are out-of-date. Starting with the v10 release of Icarus Verilog, the preferred (and supported) method of building a standalone Windows binary is to use the Mingw-w64 toolchain, as described -
Development Time Line
This page is meant to be a living document that describes current thinking for what we want to do with Icarus Verilog development. We try to divide our intentions into a release schedule of sorts -
Release Notes Icarus Verilog 0 9 4
This is an update to the Icarus Verilog 0.9 release series. If you are new to v0.9 in general, then you may want to refer back to these older release notes since this -
Release Notes Icarus Verilog 0 9 3
This is an update to the Icarus Verilog 0.9 release series. If you are new to v0.9 in general, then you may want to refer back to these older release notes since this -
GIT Branch Summary
The main git repository for Icarus Verilog is available at git@github.com:steveicarus/iverilog.git. The master branch is always the main development path for Icarus Verilog, but there are also various subordinate branches
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