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Module parameters at Compile Time[]
- This discussion was moved here from Graffiti.
It would be nice to be able to specify at compile time parameter overrides for any root modules of a design. For example, if a root module has a "parameter cpu_width = 32;" it would be nice to be able to include in the command file the line "+parameter+cpu_width=64" and have that parameter overriden in the root module. This would make for a more robust alternative to the preprocessor that is sometimes used.
This would invole some work in the core compiler (touching early elaboration code) as well as the compiler driver in order to handle the command argument itself.
--Stevewilliams 00:04, 24 March 2007 (UTC)
I second that motion! I have a need for such a feature right now.
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Why restrict yourself to just root modules? Make it a defparam that must use a full path. Of course pr1510724 would need to be addressed. A command file interface would also be nice.
--Cary 18:33, 1 November 2007 (UTC)
OK, I'll buy that, but in that case we'll have to come up with a semantic for conflicts. (This is exactly the sort of issue that leads to the SystemVerilog folks wanting to remove defparam altogether.) I think that the restricted form (only override parameters in root modules) is easier because there is only exactly one possible source of overrides for root module parameters: the command file. Underneath the root module, a command file defparam can conflict with an internal defparam, and can also have multi-path conflicts with the command file itself.
So I would do it in stages. First, support override of root module parameters only, and later add support for the more general case. If this were to be a Google Summer of Code project, I would restrict it to the root modules only case to keep the work managable, and keep the student candidate from exploding.
--Stevewilliams 03:16, 3 November 2007 (UTC)
Actually top level parameters can be set from other modules, so you have the same problem with top level modules. What you don't have is parameters being overridden at instantiation time. My assumption would be that a value from the command line/file would have precedence over a value set in the code. Here is some Verilog code to demonstrate:
module top;
parameter pval = 1;
initial $display("The parameter value is %0d.", pval);
endmodule
module defs;
defparam top.pval = 10;
endmodule
It will display 10 and not 1.
Cary 00:24, 4 November 2007 (UTC)