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Compile Multiple files in verilog
Can I ask, how I compile multiple files with icarus verilog?
I have a file "test.v" , which have 2 includes :
e.g.
`include "in1.v"
`include "in2.v"
If I do "iverilog test.v", it throws the following message :
"test.v:51: Include file in1.v not found
No top level modules, and no -s option."
I also tried "iverilog test.v ~/...absolute_path/in1.v ~/...absolute_path/in2.v" ,
but it stills shows the same message,
does anyone know what to do?