If you want to use the Xilinx libraries this should help reduce some confusion.
Simprims
Edit
Add:
iverilog -y%XILINX%/verilog/src/simprims/
or for Linux:
iverilog -y$XILINX/verilog/src/simprims/
to your iverilog command. Similarly, the unimacro and unisims directory also have modules.
Then, run vvp, and generate a VCD or ltx from your testbench.
The SIMPRIMS modules all have a `timescale directive, the glbl.v file has a different one.
